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W312-02
FTG for VIATM K7 Series Chipset with Programmable Output Frequency
Features
* Single chip FTG solution for VIATM K7 Series chipsets * Programmable clock output frequency with less than 1 MHz increment * Integrated fail-safe Watchdog timer for system recovery * Automatically switch to HW selected or SW programmed clock frequency when watchdog timer time-out * Capable of generate system RESET after a watchdog timer time-out occurs or a change in output frequency via SMBus interface * Support SMBus byte read/write and block read/ write operations to simplify system BIOS development * Vendor ID and Revision ID support * Programmable drive strength for PCI output clocks * Programmable output skew between CPU, AGP and PCI * Maximized EMI suppression using Cypress's Spread Spectrum technology * Low jitter and tightly controlled clock skew * Two pairs of differential CPU clocks * Eleven copies of PCI clocks * Three copies of 66-MHz outputs * Two copies of 48-MHz outputs * Three copies of 14.31818-MHz reference clocks * One RESET output for system recovery * Power management control support
Key Specifications
CPU Outputs Cycle-to-cycle Jitter: ............................. 250 ps 48-MHz, 3V66, PCI Outputs Cycle-to-cycle Jitter: .................................................... 500 ps CPU, 3V66 Output Skew:............................................ 200 ps 48-MHz Output Skew: ................................................. 250 ps PCI Output Skew:........................................................ 500 ps
Block Diagram
VDD_REF
Pin Configuration
REF2 REF1/FS1* REF0/FS0*
[1]
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/FS0* REF1/FS1* REF2 REF_STOP#* AGP_STOP#* GND_CPU CPUT0 CPUC0 VDD_CPU CPUT_CS CPUC_CS GND_CPU CPU_STOP#* PCI_STOP#* PD#* VDD_CORE GND_CORE SDATA SCLK GND_AGP AGP2 AGP1 AGP0 VDD_AGP
X1 X2
XTAL OSC
PLL REF FREQ
VDD_CPU
Divider, Delay, and Phase Control Logic 2
CPUT0,CPUC0 CPUT_CS,CPUC_CS VDD_AGP AGP0:2
SDATA SCLK
SMBus Logic
(FS0:4)
3
VDD_PCI PCI0/SEL24_48#*
PLL 1
PD# CPU_STOP# PCI_STOP# AGP_STOP# REF_STOP#
5
PCI1:8 PCI9_E
RST# VDD_48MHz
48MHz/FS3*
VDD_REF GND_REF X1 X2 VDD_48MHz *FS2/48MHz *FS3/24_48MHz GND_48MHz *FS4/PCI_F *SEL24_48#/PCI0 PCI1 GND_PCI PCI2 PCI3 VDD_PCI PCI4 PCI5 PCI6 GND_PCI PCI7 PCI8 PCI9_E VDD_PCI RST#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PLL2
/2 SEL24_48#*
24_48MHz/FS4*
Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
W312-02
Cypress Semiconductor Corporation Document #: 38-07259 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 28, 2005
W312-02
Pin Definitions
I
Pin Name REF0/FS0
Pin No. 48
Pin Type I/O
Pin Description Reference Clock Output 0/Frequency Select 0: 3.3V 14.318-MHz clock output. REF0 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 5. Reference Clock Output 0/Frequency Select 1: 3.3V 14.318-MHz clock output. REF1 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 5. Reference Clock Output 2: 3.3V 14.318-MHz clock output. REF2 will be disabled when REF_STOP# is active. Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. Free-Running PCI Clock/Frequency Select 4: 3.3V 33-MHz free running PCI clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 5. PCI Clock 0/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This output will be disabled when PCI_STOP# is active. This pin also serves as the select strap to determine device operating frequency of 24_48MHz output. PCI Clock 1 through 8: 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled when PCI_STOP# is active. Early PCI Clock 9: 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled when PCI_STOP# is active. AGP Clock 0 through 2: 3.3V 66-MHz clock outputs. The operating frequency is controlled by FS0:4 (see Table 5). AGP0:2 will be disabled when AGP_STOP# is active. 48-MHz Output/Frequency Selection 3: 3.3V 48-MHz non-spread spectrum output. 48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 5. 24 or 48-MHz Output/Select 24 or 48 MHz: 3.3V 24 or 48-MHz non-spread spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 5.
REF1/FS1
47
I/O
REF2 X1 X2 PCI_F/FS4
46 3 4 9
I/O I I I
PCI_0/SEL24_48#
10
I/O
PCI1:8 PCI9_E AGP0:2
11, 13, 14, 16, 17, 18, 20, 21 22 26, 27, 28
O O O
48MHz/FS2
6
I/O
24_48MHz/FS3
7
I/O
RST#
24
O Reset#: Open-drain RESET# output. (opendrain) CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock O (open- outputs for the K7 processor. They are open-drain outputs. drain) O CPU Clock Output for Chipset: CPUT_CS and CPUC_CS are the differential CPU clock outputs for the chipset. They are push-pull outputs. These outputs will be disabled when CPU_STOP# is active. CPU STOP Input: This input will disable CPUT_CS and CPUC_CS when it is active. PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active. AGP STOP Input: This input will disable AGP0:2 when it is active. REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz outputs when it is active.
CPUT0, CPUC0
42, 41
CPUT_CS, CPUC_CS CPU_STOP# PCI_STOP# AGP_STOP# REF_STOP#
39, 38
36 35 44 45
I I I I
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W312-02
Pin Definitions (continued)
Pin Name PD# SDATA SCLK VDD_CPU VDDQ_AGP VDDQ_PCI VDDQ_48MHz VDD_REF VDD_Core GND_REF, GND_48MHz, GND_PCI, GND_AGP, GND_Core, GND_CPU Pin No. 34 31 30 40 25 15, 23 5 1 33 2, 8, 29, 32, 37, 43 Pin Type I I/O I P P P P P P G Pin Description Power-Down Input: This input will trigger the clock generator into Power Down mode when it is active. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 2.5V Power Connection: Power supply for CPU output buffers. Connect to 2.5V. 3.3V Power Connection: Power supply for AGP output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for PCI output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for 48 MHz output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for reference output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for PLL core. Connect to 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
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W312-02
Serial Data Interface The W312-02 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the controller. For block write/read operation, the bytes must be Table 1. Command Code Definitions Bit 7 6:0 Descriptions 0 = Block read or block write operation 1 = Byte/Word read or byte/word write operation Byte offset for byte/word read or write operation. For block read or write operations, these bits need to be set at `0000000'. accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word write and byte read operations, system controller can access individual indexed byte. The offset of the indexed byte is encoded in the command code. .The block write and block read protocol is outlined in Table 1 while Table 2 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h)
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
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W312-02
Table 3. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits (D2) Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte low - 8 bits Acknowledge from slave Data byte high - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits (D3) Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte low from slave - 8 bits Acknowledge Data byte high from slave - 8 bits NOT acknowledge Stop Word Read Protocol Description
19 20:27 28 29:36 37 38
19 20 21:27 28 29 30:37 38 39:46 47 48
Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
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W312-02
W312-02 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# - - - - Name Spread Enable Spread Select2 Spread Select1 Spread Select0 Default 0 0 0 0 0 = Disabled 1 = Enabled `000' = 0.25% `001' = -0.5% `010' = 0.5% `011' = 0.38% `100' = Reserved `101' = Reserved `110' = Reserved `111' = Reserved Bit 3 Bit 2 Bit 1 Bit 0 Byte 1: Control Register 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 2: Control Register 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 18 17 16 14 13 11 10 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Page 6 of 20 Description Pin# 42, 41 39, 38 6 7 - 28 27 26 Name CPUT0, CPUC0 CPUT_CS, CPUC_CS 48MHz 24_48MHz Reserved AGP2 AGP1 AGP0 Default 1 1 1 1 0 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) Description - - - - SEL3 SEL2 SEL1 SEL0 0 0 0 0 SW Frequency selection bits. See Table 5. Description 2. All unused register bits (reserved and N/A) should be written to a "0" level. 3. All register bits labeled "Initialize to 0" must be written to zero during initialization.
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W312-02
\
Byte 3: Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 9 22 - 21 46 - 47 48 Name PCI_F PCI9_E Reserved PCI8 REF2 Reserved REF1 REF0 Default 1 1 0 1 1 0 1 1 (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) Description
Byte 4: Watchdog Timer Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin# - - - - - - - Name Reserved FS_Override WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 Default 0 0 1 1 1 1 1 Reserved 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches "0", it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec Description
Bit 0
-
WD_PRE_SCAL ER
0
Byte 5: Control Register 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 9 7 6 47 48 - - - Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input Reserved Reserved SEL4 Default X X X X X 0 0 0 Reserved Reserved SW Frequency selection bits. See Table 5. Description Latched FS[4:0] inputs. These bits are read only.
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W312-02
Byte 6: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 1 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description
Byte 7: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 1 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description
Byte 8: Vendor ID and Revision ID Register (Read Only) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Default 0 0 0 0 1 0 0 0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Semiconductor's Vendor ID. This bit is read only. Bit[2] of Cypress Semiconductor's Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor's Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor's Vendor ID. This bit is read only. Pin Description
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W312-02
Byte 9: System Reset and Watchdog Timer Register Bit Bit 7 Bit 6 Name Reserved PCI_DRV Default 0 0 Reserved PCI clock output drive strength 0 = Normal 1 = High Drive Reserved This bit will enable the generation of a Reset pulse when a watchdog timer timeout occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Reserved Pin Description
Bit 5 Bit 4
Reserved RST_EN_WD
0 0
Bit 3
RST_EN_FC
0
Bit 2
WD_TO_STATUS
0
Bit 1
WD_EN
0
Bit 0
Reserved
0
Byte 10: Skew Control Register Bit Bit 7 Bit 6 Bit 5 Name CPU_Skew2 CPU_Skew1 CPU_Skew0 Default 0 0 0 CPU skew control 000 = Normal 001 = -150 ps 010 = -300 ps 011 = -450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Reserved PCI skew control 00 = Normal 01 = -500 ps 10 = Reserved 11 = +500 ps AGP skew control 00 = Normal 01 = -150 ps 10 = +150 ps 11 = +300 ps Description
Bit 4 Bit 3 Bit 2
Reserved PCI_Skew1 PCI_Skew0
0 0 0
Bit 1 Bit 0
AGP_Skew1 AGP_Skew0
0 0
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W312-02
Byte 11: Recovery Frequency N - Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Default 0 0 0 0 0 0 0 0 Pin Description If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W312-02 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation.
Byte 12: Recovery Frequency M- Value Register Bit Bit 7 Name ROCV_FREQ_SEL Default 0 Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W312-02 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0
0 0 0 0 0 0 0
Byte 13: Programmable Frequency Select N-Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Default 0 0 0 0 0 0 0 0 Pin Description If Prog_Freq_EN is set, W300 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz.
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W312-02
Byte 14: Programmable Frequency Select N-Value Register Bit Bit 7 Name Pro_Freq_EN Default 0 Description Programmable output frequencies enabled 0 = disabled 1 = enabled If Prog_Freq_EN is set, W300 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0
0 0 0 0 0 0 0
Byte 15: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 16: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Byte 17: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin# - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# - - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved. Write with `1' Reserved. Write with `1' Description
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W312-02
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 156.0 154.0 152.0 147.0 144.0 142.0 138.0 136.0 124.0 122.0 117.0 115.0 113.0 108.0 105.0 102.0 Reserved Reserved Reserved 200.0 190.0 180.0 170.0 150.0 140.0 120.0 110.0 66.6 200.0 166.6 100.0 133.3 3V66 78.0 77.0 76.0 73.5 72.0 71.0 69.0 68.0 62.0 61.0 78.0 76.7 75.3 72.0 70.0 68.0 Reserved Reserved Reserved 66.6 76.0 72.0 68.0 75.0 70.0 60.0 73.3 66.6 66.6 66.6 66.6 66.6 PCI 39.0 38.5 38.0 36.8 36.0 35.5 34.5 34.0 31.0 30.5 39.0 38.3 37.7 36.0 35.0 34.0 Reserved Reserved Reserved 33.3 38.0 36.0 34.0 37.5 35.0 30.0 33.3 33.3 33.3 33.3 33.3 33.3 Output Frequency PLL Gear Constants (G) 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 Reserved Reserved Reserved 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741
Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms.
The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized inTable 7.
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W312-02
Table 6. Register Summary Name Pro_Freq_EN Programmable output frequencies enabled 0 = Disabled (default) 1 = Enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs FS_Override When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. WD_EN WD_TO_STATUS 0 = Stop and reload Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches "0", it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec Page 13 of 20 Description
ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0]
WD_TIMER[4:0]
WD_PRE_SCALER
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W312-02
Table 6. Register Summary (continued) Name RST_EN_WD Description This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled "G" stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 5. The ratio of (N+3) and (M+3) need to be greater than "1" [(N+3)/(M+3) > 1]. Table 7 lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register.
RST_EN_FC
How to Program CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) "N" and "M" are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively.
Table 7. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 50 MHz-129 MHz 130 MHz-248 MHz Gear Constants 48.00741 48.00741 Fixed Value for M-Value Register 93 48 Range of N-Value Register for Different CPU Frequency 97-255 127-245
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Absolute Maximum Ratings[2]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi.
tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TB TA ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V5% and 2.5V5%
Parameter Supply Current IDD IDD Logic Inputs VIL VIH IIL IIH VOL VOH VOL Input Low Voltage Input High Voltage Input Low Input High Current[4] Current[4] IOL = 1 mA IOH = -1 mA CPUT_CS, CPUC_CS, CPUT0, CPUC0 CPUT_CS, CPUC_CS, CPUT0, CPUC0 PCI, AGP REF 48 MHz 24_48 MHz IOH Output High Current PCI, AGP REF 48 MHz 24_48 MHz Termination to V pull-up (external) Termination to V pull-up (external) VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V 3.1 0 0.3 GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 50 V V A A mV V V 3.3V Supply Current 2.5V Supply Current CPU =100 MHz Outputs Loaded[3] CPUCS =100 MHz Outputs Loaded[3] 260 25 mA mA Description Test Condition Min. Typ. Max. Unit
Clock Outputs Output Low Voltage Output High Voltage Output Low Voltage
VOH
Output High Voltage
1.0
1.2
V
IOL
Output Low Current
70 50 50 50 70 50 50 50
110 70 70 70 110 70 70 70
135 100 100 100 135 100 100 100
mA mA mA mA mA mA mA mA
Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 4. X1 input threshold voltage (typical) is VDD/2.
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W312-02
DC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V5% and 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[4] Load Capacitance, Imposed on External Crystal[5] X1 Input Capacitance[6] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDD = 3.3V 1.65 18 TBD 5 6 7 V pF pF pF pF nH Description Test Condition Min. Typ. Max. Unit
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[7] CPU = 100 MHz Parameter tR tF tD tJC fST Description Output Fall Edge Rate Duty Cycle Jitter, Cycle to Cycle Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short from Power-up (cold cycles exist prior to frequency start) stabilization. AC Output Impedance VO = VX 3 Test Condition/Comments CPU_CS Measured at 50% point Min. 1.0 1.0 45 Typ. Max. 4.0 4.0 55 250 3 Output Rise Edge Rate CPU_CS CPU = 133 MHz Min. 1.0 1.0 45 Typ. Max. 4.0 4.0 55 250 Unit V/ns V/ns % ps ms
Zo
50
50
Notes: 5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Refer to Figure 1 for K7 operation clock driver test circuit.
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PCI Clock Outputs (Lump Capacitance Test Load = 30 pF) Parameter tP tH tL tR tF tD tJC tSK tO fST Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Description Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ms
Frequency Stabilization Assumes full supply voltage reached within 1 ms from from Power-up (cold start) power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 30
Zo
REF Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Frequency Stabilization from Assumes full supply voltage reached within 1 ms Power-up (cold start) from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 40
Zo
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
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24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 24 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 - 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 24.004 +167 57/34 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
VDD + V1 3.3 Z0 = 52 Length = 5" T1 Z0 = 52 Length = 3" T2
1.5V
R1 68
CPUCLK_T
R8 47
20p
1.5V
Clock Chip CPUDriver
R3 68 Z0 = 52 Length = 5" T4 Z0 = 52 Length = 3" T5 20p
CPUCLK_C
R9 47
Figure 1. K7 Open Drain Clock Driver Test Circuit
Ordering Information
Ordering Code W312-02H W312-02HT Lead-free CYW312OXC CYW312OXCT 48-pin SSOP 48-pin SSOP - Tape and Reel Commercial, 0C to 70C Commercial, 0C to 70C 48-pin SSOP 48-pin SSOP - Tape and Reel Package Type Product Flow Commercial, 0C to 70C Commercial, 0C to 70C
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W312-02
Package Drawing and Dimension
48-Lead Shrunk Small Outline Package O48
51-85061-*C
VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
W312-02
Document History Page
Document Title: W312-02 FTG for VIATM K7 Series Chipset with Programmable Output Frequency Document Number: 38-07259 REV. ** *A ECN NO. 110524 118014 Issue Date 01/07/02 09/13/02 Orig. of Change SZV RGL Description of Change Change from Spec number: 38-01087 to 38-07259 Changed the KT266 word to K7 Series in the title and features in page 1. Filled up all the missing Byte # and Byte heading description on all the serial configuration tables on pages 6-12. Replaced the package drawing and dimension as per CY standard. Removed the word "PRELIMINARY" Added power-up requirements to maximum ratings information. Added Lead-free devices
*B *C
122860 358435
12/19/02 See ECN
RBI RGL
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